ELECTROPLATED SOLDER ALLOYS FOR FLIP-CHIP INTERCONNECTIONS

Flip chip mounting of bare dice is gaining widespread use in microelec tronics packaging. The main drivers for this technology are high packa ging density, improved performance at high frequency, low parasitic ef fects and potentially high reliability and low cost. Many companies ha ve made significant efforts to develop a technology for bump processin g, bare die testing and underfill encapsulation to gain the benefit of all potential advantages. We have focussed on low cost bumping of ful ly processed silicon wafers to develop a flexible scheme for various r eflow requirements. The bumping process is based on galvanic plating f rom an alloy solution or, alternatively, from several elemental platin g baths. Sputtered Mo/Cu or Cr/Cu is used as a wettable base for elect roplating. Excess base metal is removed by using the bumps as an etchi ng mask. Variation of the alloy composition or the layer structure, al lows the adjustment of the bump reflow temperature for the specific re quirements of the assembly. Using binary tin-lead and ternary tin-lead -bismuth alloys, reflow temperatures from 100 degrees C (bismuth rich alloys) to above 300 degrees C (lead rich alloys) can be covered. The influence of the plating current density on the final alloy compositio n has been established by ion beam analysis of the plated layers and a series of reflow experiments. To control the plating uniformity and t he alloy composition, a new cup plating system has been built with a r andom flow pattern and continuous adjustment of the current density. A well-controlled reflow of the bumps has been achieved in hot glycerol up to the eutectic point of tin-lead alloys. For high temperature all oys, high molecular weight organic liquids have been used. A tensile p ull strength of 20 g per bump and resistance of 5 m Omega per bump hav e been measured for typical eutectic tin-lead bumps of 100 mu m in dia meter.