SMART-PIXEL CELLULAR NEURAL NETWORKS IN ANALOG CURRENT-MODE CMOS TECHNOLOGY

This paper presents a systematic approach to design CMOS chips with co ncurrent picture acquisition and processing capabilities. These chips consist of regular arrangements of elementary units, called smart pixe ls. Light detection is made with vertical CMOS-BJT's connected in a Da rlington structure. Pixel smartness is achieved by exploiting the Cell ular Neural Network paradigm [1], [2], incorporating at each pixel loc ation an analog computing cell which interacts with those of nearby pi xels. We propose a current-mode implementation technique and give meas urements from two 16 x 16 prototypes in a single-poly double-metal CMO S n-well 1.6-mum technology. In addition to the sensory and processing circuitry, both chips incorporate light-adaptation circuitry for auto matic contrast adjustment. They obtain smart-pixel densities up to 89 units/mm2, with a power consumption down to 105 muW/unit and image pro cessing times below 2 mus.