A 10-BIT PIPELINED SWITCHED-CURRENT A D CONVERTER/

A modified RSD algorithm has been implemented in a switched-current pi pelined A/D converter. The offset insensitivity of the RSD converter r educes the effect of several nonidealities proper to current copier ce lls. Moreover, the benefits resulting from the large tolerances inhere nt to the RSD algorithm and the pipelined architecture result in an im proved conversion rate. Measurements on a first prototype give an inte gral nonlinearity error less than 0.8 LSB for 10-bit accuracy. Power d issipation is 20 mW and silicon area is 2.5 mm2. The measured sampling rate is 550 kS/s. It is an improvement by a factor-of twenty compared to known equivalent CMOS switched-current converters. It is neverthel ess still well below the predicted conversion rate of 4.5 MHz, which s hould be obtained once this A/D converter is integrated into an analog front-end. Full compatibility with standard digital technologies make s this kind of converter attractive for low power, medium-fast convert ers with 10-bit accuracy.