A HIGH-SPEED PROGRAMMABLE CMOS INTERFACE SYSTEM COMBINING D A CONVERSION AND FIR FILTERING/

This paper describes the design, integrated circuit realization, and e xperimental characterization of a high-speed programmable interface sy stem combining the functions of digital-to-analog (D/A) conversion and FIR filtering. The system comprises four high-speed digital delay lin es, with programmable delay length, together with four high-speed stee ring-current D/A converters with independent digitally-programmable ga ins. A demonstration prototype chip has been fabricated in a 1.2-mum d igital CMOS technology. At 54 MHz conversion rate and digital delay li nes clocked at 18 MHz, it consumes 115 mW for a full-scale output curr ent of 13.3 mA at 5 V supply.