AN 8-BIT MULTITASK MICROPOWER RISC CORE

This paper describes a multitask micropower RISC core. A hardware sche duler handles up to four separate tasks in a pseudo-parallel way. Task or context switching is performed at the instruction level and does n ot need additional instructions. In a 1.5-V low-power 2-mum technology the core area is 5-6 mm2, depending upon the global routing of the co mplete ASIC. Measured power consumption is 0.2 muA/kHz at 1.5 V with a low-power 8-K word ROM and a 256-byte RAM.