7.5-GB S MONOLITHICALLY INTEGRATED CLOCK RECOVERY CIRCUIT USING PLL AND 0.3-MU-M GATE LENGTH QUANTUM-WELL HEMTS/

A monolithically integrated clock recovery (CR) circuit making use of the phase-locked loop (PLL) circuit technique and enhancement/depletio n AlGaAs/GaAs quantum well-high electron mobility transistors (QW-HEMT 's) with gate lengths of 0.3 mum has been realized. A novel preprocess ing circuit was used. In the PLL a fully-balanced varactorless VCO was applied. The VCO has a center oscillating frequency of about 7.7 GHz and a tuning range greater than 500 MHz. A satisfactory clock signal h as been obtained at a bit rate of about 7.5 Gb/s. The power consumptio n is less than 200 mW at a supply voltage of -5 V.