POWER EFFICIENT TECHNOLOGY DECOMPOSITION AND MAPPING UNDER AN EXTENDED POWER-CONSUMPTION MODEL

We propose a new power consumption model that accounts for the power c onsumption at the internal nodes of a CMOS gate. Next, we address the problem of minimizing the average power consumption during the technol ogy dependent phase of logic synthesis. Our approach consists of two s teps. In the first step, we generate a NAND decomposition of an optimi zed Boolean network such that the sum of average switching rates for a ll nodes in the network is minimum. In the second step, we perform a p ower efficient technology mapping that finds a minimal power mapping f or given timing constraints (subject to the unknown load problem).