IMPROVED ARRAY ARCHITECTURES OF DINOR FOR 0.5 MU-M 32 M AND 64 MBIT FLASH MEMORIES

A novel operation of a flash memory cell, named DINOR (DIvided bit lin e NOR) operation, is proposed. This operation is based on gate-biased FN programming/FN erasing, and we found that it satisfies all basic ce ll characteristics such as program/erase, disturb immunity and a cycli ng endurance. Making a good use of this cell operation, we also propos ed a new array structure applied to DINOR type cell whose bit line is divided into the main and sub bit line, having 1.82 mum2 cell size, su itable for 32 Mbit flash memory based on 0.5 mum CMOS process. In the last part of this paper, the useful and practical application of the D INOR operation to a virtual ground array architecture, realizing 1.0 m um2 cell size for a 0.5 mum 64 Mbit flash memory, is described.