PATDRAM - PIXEL-ALIGNED TRIPLE-PORT DRAM

This paper describes the architecture and new circuit technologies of a proposed Pixel (bit) -Aligned Tripleport DRAM (PATDRAM). The PATDRAM has a 270 K word x 16 b Random Access Memory (RAM), a 512 word x 8 b Serial Access Memory-(a) (SAMa) and a 1024 word x 4 b Serial Access Me mory-(b) (SAMb). The random port, serial-a and serial-b port can be op erated by three independent synchronous clocks. In these three ports, word data can be aligned to the location of an arbitrary bit position. Data transfer from SAMb to RAM can be individually masked by transfer mask data. The RAM operates by 33 MHz synchronous clock and two SAMs operate by 40 MHz clocks. Novel architecture of the PATDRAM accelerate s graphics performance and simplifies in multimedia systems which mana ge both realtime video and computer graphics data, and also accelerate s graphics performance in both two-dimensional (2D) and three-dimensio nal (3D) graphics systems. PATDRAM was designed using a 0.6 mu double metal, triple poly, stacked capacitor, CMOS process technology in a 10 .98 mm x 9.88 mm die area integrated 4.4 Mb RAM, 8 Kb SAM, 4 Kb transf er mask register and 5 Kgate logic.