T. Sugibayashi et al., A DISTRIBUTIVE SERIAL MULTIBIT PARALLEL TEST SCHEME FOR LARGE-CAPACITY DRAMS, IEICE transactions on electronics, E77C(8), 1994, pp. 1323-1327
A distributive serial multi-bit parallel test scheme for large capacit
y DRAMs has been developed. The scheme, distributively and serially, e
xtracts and compares the data from cells on a main word-line. This tes
t scheme features a high parallel test bit number, little restriction
on test patterns, and, with regard to cells and sense-amplifiers, the
same operational margin as normal mode. In an experimental 256-Mb DRAM
, the scheme successfully has achieved a 512-bit parallel test.