A DISTRIBUTIVE SERIAL MULTIBIT PARALLEL TEST SCHEME FOR LARGE-CAPACITY DRAMS

Citation
T. Sugibayashi et al., A DISTRIBUTIVE SERIAL MULTIBIT PARALLEL TEST SCHEME FOR LARGE-CAPACITY DRAMS, IEICE transactions on electronics, E77C(8), 1994, pp. 1323-1327
Citations number
NO
Categorie Soggetti
Engineering, Eletrical & Electronic
ISSN journal
09168524
Volume
E77C
Issue
8
Year of publication
1994
Pages
1323 - 1327
Database
ISI
SICI code
0916-8524(1994)E77C:8<1323:ADSMPT>2.0.ZU;2-0
Abstract
A distributive serial multi-bit parallel test scheme for large capacit y DRAMs has been developed. The scheme, distributively and serially, e xtracts and compares the data from cells on a main word-line. This tes t scheme features a high parallel test bit number, little restriction on test patterns, and, with regard to cells and sense-amplifiers, the same operational margin as normal mode. In an experimental 256-Mb DRAM , the scheme successfully has achieved a 512-bit parallel test.