A 180 MHZ MULTIPLE-REGISTERED 16 MBIT SDRAM WITH FLEXIBLE TIMING SCHEME
Citation
H. Iwamoto et al., A 180 MHZ MULTIPLE-REGISTERED 16 MBIT SDRAM WITH FLEXIBLE TIMING SCHEME, IEICE transactions on electronics, E77C(8), 1994, pp. 1328-1333
Categorie Soggetti
Engineering, Eletrical & Electronic
SICI code
0916-8524(1994)E77C:8<1328:A1MM1M>2.0.ZU;2-8
Abstract
A multiple-registered architecture is described for 180 MHz 16 Mbit sy
nchronous DRAM. The proposed architecture realizes a flexible control
of critical timings such as I/O line busy time and achieves an operati
on at 180 MHz clock rate with area penalty of only 5.4% over the conve
ntional DRAM.
