A BIPOLAR-BASED 0.5 MU-M BICMOS TECHNOLOGY ON BONDED SOI FOR HIGH-SPEED LSIS

Authors
YOSHIDA M HIRAMOTO T FUJIWARA T HASHIMOTO T MURAYA T MURATA S WATANABE K TAMBA N IKEDA T
Citation
M. Yoshida et al., A BIPOLAR-BASED 0.5 MU-M BICMOS TECHNOLOGY ON BONDED SOI FOR HIGH-SPEED LSIS, IEICE transactions on electronics, E77C(8), 1994, pp. 1395-1403
Citations number
NO
Categorie Soggetti
Engineering, Eletrical & Electronic
Journal title
IEICE transactions on electronics → ACNP
ISSN journal
09168524
Volume
E77C
Issue
8
Year of publication
1994
Pages
1395 - 1403
Database
ISI
SICI code
0916-8524(1994)E77C:8<1395:AB0MBT>2.0.ZU;2-P
Abstract
A new BiCMOS process based on a high-speed bipolar process with 0.5 mu m emitter width has been developed using a bonded SOI substrate. Doubl e polysilicon bipolar transistors with the trench isolation, shallow j unctions and the pedestal collector implantation provide a high cut-of f frequency of 27 GHz. Stress induced device degradation is carefully examined and a low stress trench isolation process is proposed.