THE 150 NS DETECTOR PROJECT - PROTOTYPE PREAMPLIFIER RESULTS

The long-term goal of the 150 ns detector project is to develop a pixe l area detector capable of 6 MHz frame rates (150 ns/frame). Our miles tones toward this goal are: a single pixel, 1 x 256 1D and 8 x 8 2D de tectors, 256 x 256 2D detectors and, finally, 1024 x 1024 2D detectors . The design strategy is to supply a complete electronics chain (reset ting preamp, selectable gain amplifier, analog-to-digital converter (A DC), and memory) for each pixel. In the final detectors these will all be custom integrated circuits. The front-end preamplifiers are integr ated first, since their design and performance are the most unusual an d also critical to the project's success. Similarly, our early work is concentrated on devising and perfecting detector structures. In this paper we demonstrate the performance of prototypes of our integrated p reamplifiers. While the final design will have 64 preamps to a chip, i ncluding a switchable gain stage, the prototypes were integrated 8 cha nnels to a ''Tiny Chip'' and tested in 4 configurations (feedback capa citor Cf equal 2.5 or 4.0 pF, output directly or through a source foll ower). These devices have been tested thoroughly for reset settling ti mes, gain, linearity, and electronic noise. They generally work as des igned, being fast enough to easily integrate detector charge, settle, and reset in 150 ns. Gain and linearity appear to be acceptable. Curre nt values of electronic noise, in double-sampling mode, are about twic e the design goal of 2/3 of a single photon at 6 keV. We expect this f igure to improve with the addition of the onboard amplifier stage and improved packaging. Our next test chip will include these improvements and allow testing with our first detector samples, which will be 1 x 256 (50 mum wide pixels) and 8 x 8 (1 mm2 pixels) element detector on 1 mm thick silicon.