A MONOLITHIC PROCESSING SUBSYSTEM

Authors
BREWER JE MILLER LG GILBERT IH MELIA JF GARDE D DEMARIS JE
Citation
Je. Brewer et al., A MONOLITHIC PROCESSING SUBSYSTEM, IEEE transactions on components, packaging, and manufacturing technology. Part B, Advanced packaging, 17(3), 1994, pp. 310-317
Citations number
8
Categorie Soggetti
Engineering, Eletrical & Electronic","Engineering, Manufacturing","Material Science
Journal title
IEEE transactions on components, packaging, and manufacturing technology. Part B, Advanced packaging → ACNP
ISSN journal
10709894
Volume
17
Issue
3
Year of publication
1994
Pages
310 - 317
Database
ISI
SICI code
1070-9894(1994)17:3<310:AMPS>2.0.ZU;2-Y
Abstract
A single-chip 120 MFLOP (peak) 26 million transistor digital processin g subsystem with 512 kilobytes of on-chip SRAM has been developed. Thi s general purpose 32-bit floating point Harvard architecture device, w hich incorporates sophisticated communication capabilities and at maxi mum throughput dissipates less than 2 W, can be used as a stand-alone processor or as a building block for both SIMD and MIMD processor arra ys. This paper describes physical and functional features of the chip, and provides some discussion of how it can be applied.