AN ARCHITECTURAL APPROACH FOR INCREASING CLOCK FREQUENCY AND COMMUNICATION SPEED IN MONOLITHIC WSI SYSTEMS

Based on a special pipelining technique, a new methodology for increas ing the clock frequency and communication speed in monolithic WSI syst ems is proposed. SPICE simulations show that the clock frequency on a synchronous wafer-scale system, implemented using a 1.2 mum CMOS techn ology, can be operated well above 140 MHz, which is approximately five times the maximum frequency of current systems [1]. It is also shown that frequencies higher than 1 GHz can be achieved if the technique is pushed to its limits. The methodology can be applied to interconnecti on networks as well, thereby improving their speed by approximately th e same factor. In order to assess the various design tradeoffs imposed by the technique, a prototype communication interface has been design ed using 1.2 mum CMOS standard cells. This interface is intended to be used in a special distributed-queue, dual-bus (DQDB) communication ne twork.