DEEP-SUBMICROMETER CHANNEL DESIGN IN SILICON-ON-INSULATOR (SOI) MOSFETS (VOL 15, PG 183, 1994)

Citation
Lt. Su et al., DEEP-SUBMICROMETER CHANNEL DESIGN IN SILICON-ON-INSULATOR (SOI) MOSFETS (VOL 15, PG 183, 1994), IEEE electron device letters, 15(9), 1994, pp. 366-369
Citations number
10
Categorie Soggetti
Engineering, Eletrical & Electronic
ISSN journal
07413106
Volume
15
Issue
9
Year of publication
1994
Pages
366 - 369
Database
ISI
SICI code
0741-3106(1994)15:9<366:DCDIS(>2.0.ZU;2-9
Abstract
Short-channel effects in deep-submicrometer SOI MOSFET's are explored over a wide range of device parameters using two-dimensional numerical simulations. To obtain reduced short-channel effects in SOI over bulk technologies, the silicon film thickness must be considerably smaller than the bulk junction depth because of an additional charge-sharing phenomenon through the SOI buried oxide. The optimal design space, con sidering nominal and short-channel threshold voltage, shows ample desi gn options for both fully and partially depleted devices, however, man ufacturing considerations in the 0.1 mum regime may favor partially de pleted devices.