MULTIPLE-FAULT DETECTION IN PARITY CHECKERS

Authors
Citation
Wb. Jone et Cj. Wu, MULTIPLE-FAULT DETECTION IN PARITY CHECKERS, I.E.E.E. transactions on computers, 43(9), 1994, pp. 1096-1099
Citations number
12
Categorie Soggetti
Computer Sciences","Engineering, Eletrical & Electronic","Computer Science Hardware & Architecture
ISSN journal
00189340
Volume
43
Issue
9
Year of publication
1994
Pages
1096 - 1099
Database
ISI
SICI code
0018-9340(1994)43:9<1096:MDIPC>2.0.ZU;2-Y
Abstract
Parity checkers are widely used in digital systems to detect errors wh en systems are in operation. Since parity checkers are monitoring circ uits, their reliability must be guaranteed by performing a thorough te sting. In this work, multiple fault detection of parity checkers is in vestigated. We have found that all multiple stuck-at faults occurring on a parity tree can be completely detected using test patterns provid ed by the identity matrix plus zero vector. The identity matrix contai ns 1's on the main diagonal and 0's elsewhere; while the zero vector c ontains 0's. The identity matrix vectors can also detect all multiple general bridging faults, if the bridgings result in a wired-AND effect . However, test patterns generated from the identity matrix and binary matrix are required to detect a majority of the multiple bridging fau lts which yield wired-OR connections. Note that the binary matrix cont ains two 1's at each column of the matrix.