DYNAMIC COMPUTATIONAL BLOCKS FOR BIT-LEVEL SYSTOLIC ARRAYS

Integrated dynamic logic trees with latches provide cost effective cir cuit techniques for building massively pipelined, systolic, computatio nal blocks operating at the bit level. Recent results have demonstrate d that dynamic pipelines are capable of very high switching speeds wit h appropriate circuit design techniques. In this paper we trade some o f this speed for much higher functionality of each logic block. The re sulting throughput rate remains sufficiently high for useful applicati ons, but results in substantial area and power savings. Design techniq ues for the individual logic trees (switching trees) are based on simp le graph theoretic rules. Examples are shown to support the technique.