AN ACCURATE ANALYTICAL PROPAGATION DELAY MODEL FOR HIGH-SPEED CML BIPOLAR CIRCUITS

A new analytical delay model for high-speed CML circuits is presented. It is applicable to high-speed/low-voltage-swing silicon and HBT CML circuits operating at medium or high current densities. The model is b ased on bipolar SPICE parameters file, and can be used to estimate the propagation delay time of CML circuits under different operating cond itions. The detailed transient analysis accounts for delay components due to each element in the complete SPICE bipolar transistor model. Th e comparison to SPICE circuit simulation results show excellent agreem ent for a wide range of state-of-the-art technologies and circuit para meters. The new model predicts the delay time with less than 5% error in most cases. The influence of the finite slopes (slewing rate) of th e input signal and the device dimensions is also investigated. The del ay model determined the optimum current i0 (or load resistor R(L) for a transistor of a certain emitter area when driven by a source of a vo ltage swing (DELTAV) and slew time (t(r). At a specified power dissipa tion, the delay model is used to optimally size the transistor emitter area for maximum switching speed. The model provides circuit and devi ce guidelines to minimize the propagation delay time and improve the p erformance of high-speed CML circuits.