We present a new method of modeling the output conductance dispersion
of GaAs MESFET's. High frequency model parameters are extracted and th
en used to model high frequency output conductance over a wide range o
f bias conditions. The model is then used to simulate and analyze the
effect of output conductance dispersion on the performance of DCFL and
SCFL logic gates. Whereas the DCFL performance is not significantly a
ffected by the high frequency effects, the noise margin of SCFL decrea
ses by almost a factor of 30% above 100 kHz, with an associated decrea
se in the voltage swing and gate delay.