FASTBUS STANDARD ROUTINES IMPLEMENTATION FOR FERMILAB EMBEDDED PROCESSOR BOARDS

Citation
M. Votava et al., FASTBUS STANDARD ROUTINES IMPLEMENTATION FOR FERMILAB EMBEDDED PROCESSOR BOARDS, IEEE transactions on nuclear science, 41(1), 1994, pp. 165-168
Citations number
5
Categorie Soggetti
Nuclear Sciences & Tecnology","Engineering, Eletrical & Electronic
ISSN journal
00189499
Volume
41
Issue
1
Year of publication
1994
Part
1
Pages
165 - 168
Database
ISI
SICI code
0018-9499(1994)41:1<165:FSRIFF>2.0.ZU;2-G
Abstract
In collaboration with CEBAF, Fermilab has produced a new C implementat ion of the IEEE FASTBUS Standard Routines[1]1. This implementation run s under the VxWorks2 operating system and has been ported to the PC-4 revision of the FASTBUS Smart Crate Controller (FSCC)[2] and the FASTB US Readout Controller (FRC)[3]. Both of these boards are used in fixed target and collider HEP experiments. Features of this implementation include: optional generation of high-speed in-line code, built-in RPC (remote producedure call) support, and a TCL(tool command language) [4 ]command line interpreter interface. We describe this software with re cent extensions to support RPC.