HIGH-DENSITY ZERO SUPPRESSOR AND ENCODER VME BOARD USING FIELD-PROGRAMMABLE GATE ARRAY

We describe a 96 bit zero-suppressor and encoder VME board designed fo r the RPC trigger system of the L3 Forward/Backward Muon detector at C ERN. Running at 20 MHz clock frequency, the board processes the elemen tary 96 bit wide detector pattern in less than one microsecond, storin g hit addresses in a FIFO array. Details of the board architecture - b ased on seven XELINX XC3020 LCAs - are presented and simulation and pr eliminary test results are briefly reported.