A MASSIVELY-PARALLEL TRACK-FINDING SYSTEM FOR THE LEVEL-2 TRIGGER IN THE CLAS DETECTOR AT CEBAF

The track segment finding subsystem of the LEVEL 2 trigger in the CLAS detector has been designed and prototyped. Track segments will be fou nd in the 35,076 wires of the drift chambers using a massively paralle l array of 768 Xilinx XC4005 FPGA's. These FPGA's are located on daugh ter cards attached to the front-end boards distributed around the dete ctor. Each chip is responsible for finding tracks passing through a 4 x 6 slice of an axial superlayer, and reports two 'segment found' bits , one for each pair of cells. The algorithm used finds segments even w hen one or two layers or cells along the track is missing (this number is programmable), while being highly resistant to false segments aris ing from noise hits. Adjacent chips share data to find tracks crossing cell and board boundaries. For maximum speed, fully combinatorial log ic is used inside each chip, with the result that all segments in the detector are found within 150 ns. Segment collection boards gather tra ck segments from each axial superlayer and pass them via a high speed link to the segment linking subsystem in an additional 400 ns for typi cal events. The Xilinx chips are ram-based and therefore reprogrammabl e, allowing for future upgrades and algorithm enhancements.