A PROBABILISTIC TIMING APPROACH TO HOT-CARRIER EFFECT ESTIMATION

In this paper, a new approach is presented for estimating the hot-carr ier induced degradation in MOS transistors in VLSI circuits. With the decrease in feature size, many long-term reliability issues, such as H CE (Hot-Carrier Effect), TDDB (Time-Dependent Dielectric Breakdown), e tc., can no longer be ignored during the design process. In this work we mainly concentrate on BCE; however, the approach can be applied to investigate other reliability issues. HCE is a long-term reliability i ssue that is caused by the cumulative effects of all possible inputs o n the devices in the circuit over time. Existing techniques use determ inistic circuit or timing simulation to estimate HCE and fry to predic t the age of the design by incorporating device degradation over time. As a result, all HCE simulators are too slow (especially if linked to SPICE-circuit simulators) for large circuits; and even when fast simu lation techniques are used, user-specified deterministic input wavefor m are needed and, hence, the results can only represent a small sample of operating conditions. In this paper, we propose a probabilistic ti ming approach. The advantage of probabilistic simulation is that we ca n explore the cumulative effects of all possible input waveform combin ations in one run. The approach has been implemented in a general-purp ose simulator and tested on a number of typical examples and benchmark s.