LOGIC SYNTHESIS FOR FIELD-PROGRAMMABLE GATE ARRAYS

In this paper, we consider the problem of configuring Field Programmab le Gate Arrays (FPGA's) so that some given function is computed by the device. Obtaining the information necessary to configure a FPGA entai ls both logic synthesis and logic embedding. Due to the very constrain ed nature of the embedding process, this problem differs from traditio nal multilevel logic synthesis in that the structure (or lack thereof) of the synthesized logic is much more important. Furthermore, a metri c-like literal count is much less important. We present a communicatio n complexity-based decomposition technique that appears to be more sui table for FPGA synthesis than other multilevel logic synthesis methods . The key is that our logic optimization technique based on reducing c ommunication complexity is good enough to allow a simple technology ma pping to work well for FPGA devices.