THE 150 NS DETECTOR PROJECT - PROGRESS WITH SMALL DETECTORS

This project's long term goal is to develop a pixel area detector capa ble of 6 MHz frame rates (150 ns/frame). Our milestones toward this go al are: a single pixel, 1 x 256 1D and 8 x 8 2D detectors, 256 x 256 2 D detectors and, finally, 1024 x 1024 2D detectors. The design strateg y is to supply a complete electronics chain (resetting preamp, selecta ble gain amplifier, analog-to-digital converter (ADC), and memory) for each pixel. In the final detectors these will all be custom integrate d circuits. The front end preamplifiers are being integrated first, si nce their design and performance are both the most unusual and also cr itical to the project's success. Similarly, our early work is also con centrating on devising and perfecting detector structures which are th ick enough (1 mm) to absorb over 99% of the incident X-rays in the ene rgy range of interest. In this paper we discuss our progress toward th e 1 x 256 1D and 8 x 8 2D detectors. We have fabricated sample detecto rs at Stanford's Center for Integrated Systems and are preparing both to test them individually and to wirebond them to the preamplifier sam ples to produce our first working small 1D and 2D detectors. We will d escribe our solutions to the design problems associated with collectin g charge in less than 30 ns from 1 mm thick pixels in high resistivity silicon. We have constructed and tested the front end of our preampli fier design using a commercial 1.2 mum CMOS technology and are moving on to produce a few channels of the complete preamplifier, including a switchable gain stage and output stage. We will discuss both the prea mplifier design and our initial test results.