A SCALABLE DISTRIBUTED SHARED-MEMORY ARCHITECTURE

Scalability of a multiprocessor architecture depends on its ability to manage interconnection network latency with increasing number of proc essors. Interconnection network latency can be minimized by reducing t he distance traversed by a message in terms of number of nodes and wir e lengths. Scalability of a DSM architecture also depends on the scala bility of the coherency protocol and the associated directory storage requirements. In this paper we describe a DSM architecture based on a fat tree interconnection network with augmented switching nodes. The p roposed architecture is CC-NUMA, but supports several important featur es of COMA architectures. The scalability of this architecture is enha nced by integrating routing and cache coherency operations, which help s in improving locality by trapping requests locally. Scalability of a DSM architecture is defined and evaluated in terms of the asymptotic speedup of an algorithm with increasing number of processors. (C) 1994 Academic Press, Inc.