LOW OVERHEAD DESIGN FOR PROGRAMMABLE LOGIC ARRAY WITH TESTABILITY

Authors
WEI KC SHEU JJ LIU BD
Citation
Kc. Wei et al., LOW OVERHEAD DESIGN FOR PROGRAMMABLE LOGIC ARRAY WITH TESTABILITY, International journal of electronics, 77(2), 1994, pp. 241-250
Citations number
11
Categorie Soggetti
Engineering, Eletrical & Electronic
Journal title
International journal of electronics → ACNP
ISSN journal
00207217
Volume
77
Issue
2
Year of publication
1994
Pages
241 - 250
Database
ISI
SICI code
0020-7217(1994)77:2<241:LODFPL>2.0.ZU;2-U
Abstract
A new design to reduce the overhead required for a fully testable PLA is proposed. This design rearranges and groups the product lines into partitions. Then, one extra output line per partition is added to make the whole PLA testable. The silicon area overhead required by this de sign is significantly less than those of previous methods.