AN 8-BIT 200 MS S 500 MW BICMOS ADC

Authors
NISHIDA Y SONE K AMANO K MATSUBA S YUKAWA A
Citation
Y. Nishida et al., AN 8-BIT 200 MS S 500 MW BICMOS ADC, IEICE transactions on fundamentals of electronics, communications and computer science, E80A(2), 1997, pp. 328-333
Citations number
9
Categorie Soggetti
Engineering, Eletrical & Electronic","Computer Science Hardware & Architecture","Computer Science Information Systems
Journal title
IEICE transactions on fundamentals of electronics, communications and computer science → ACNP
ISSN journal
09168508
Volume
E80A
Issue
2
Year of publication
1997
Pages
328 - 333
Database
ISI
SICI code
0916-8508(1997)E80A:2<328:A82MS5>2.0.ZU;2-X
Abstract
This paper presents an 8-bit 200 M-sample/s (Ms/s) analog-to-digital c onverter (ADC) applicable to liquid crystal display (LCD) driver syste ms. The ADC features such circuit techniques as a low-power and high-s peed comparator, an open-loop sample-and-hold amplifier with a 3.4-ns acquisition time, a fully differential two-step architecture, and a re plica circuit. It is fabricated with a 0.8-mu m BICMOS process onto an area of only 12 mm(2) and it dissipates 500 mW from a single -5.2 V p ower supply.