IMPACT OF POLYSILICON DRY-ETCHING ON 0.5-MU-M NMOS TRANSISTOR PERFORMANCE - THE PRESENCE OF BOTH PLASMA BOMBARDMENT DAMAGE AND PLASMA CHARGING DAMAGE

Two types of damage mechanisms resulting from polysilicon gate dry etc hing are identified in 0.5 mum NMOS transistors. One type of damage is found to be active even after full processing and to result in positi ve charge at the edge of the gate oxide. It is found to have no correl ation with polysilicon antenna ratio and to be attributable to direct plasma bombardment. The other type of damage is found to be passivated after full processing but it is activated by electrical stress. After activation, this damage is an increasing function of polysilicon ante nna ratio as well as overetch percentage. This second type of damage i s attributable to plasma charging.