AN ARCHITECTURE FOR HIGH-PERFORMANCE SMALL-AREA MULTIPLIERS FOR USE IN DIGITAL FILTERING APPLICATIONS

A multiplier architecture and encoding scheme well suited for programm able digital filtering applications in described. The multiplier's par tial product recoding scheme uses only simple multiplexers and takes a dvantage of a RAM that stores filter coefficients. We use an optimized 20-transistor full-adder cell in the carry-save adder array, and a ca rry-select vector-merge adder produces the final output. An integrated circuit comprising an 11-b by 11-b multiplier using second-order reco ding has been fabricated in 2-mum CMOS technology. It operates in 22 n s and its core occupies 1.53 mm2. Also, an 11-b by 16-b multiplier usi ng third-order recoding has been fabricated through MOSIS in 1.2-mum C MOS technology. Its core occupies 0.9 mm2 and it operates in 19 ns.