DESIGN RULE RELAXATION APPROACH FOR HIGH-DENSITY DRAMS

A design rule relaxation approach is one of the most important require ments for high density DRAMs. The approach relaxes the design rule of a element in comparison with the memory cell size and provides high de nsity DRAMs with the minimum development of a scaled-down MOS structur e and a fine patterning lithography process. This paper describes two design rule relaxation approaches, a close-packed folded (CPF) bit-lin e cell array layout and a Boosted Dual Word-Line scheme. The CPF cell array provides 1.26 times wider active area pitch and maximum 1.5 time s wider isolation width. The Boosted Dual Word-Line scheme provides 2n times wider 1st Al pitch on memory cell array, double word-line drive r pitch and 1.5 times larger design rule for 1st Al and contacts under 1st Al. Especially wide design rule of the Boosted Dual Word-Line sch eme provides several times depth of focus (DOF) for 1st Al wiring whic h gives several times higher storage node and larger capacitance for c apacitor over bit-line (COB) stacked capacitor cells. These approaches are successfully implemented in a 4 Mb DRAM test chip with a 0.9 x 1. 8 mum2 memory cell.