TI SALICIDE PROCESS FOR SUBQUARTER-MICRON CMOS DEVICES

Using Ti self-aligned silicide (salicide) process, we fabricated subqu arter-micron complementary metal-oxide semiconductor (CMOS) devices, a nd studied the mechanism of increasing resistivity of TiSi2 on poly-Si gates from 0.075 to 20 mum long and 10 mum wide. In the gates less th an 0.1 mum long, we found that agglomeration of TiSi2 takes place duri ng low temperature annealing at 675-degrees-C for 30 seconds leading t o discontinuous TiSi2 lines. The discontinuity of TiSi2 abruptly incre ases the gate resistance, and remarkably reduces the circuit speed of CMOS ring oscillators. On the other hand, Raman spectroscopy reveals t hat the phase transition from high-resistivity C49 to low-resistivity C54 occurs in plane TiSi2 by annealing at 800-degrees-C for 30 seconds , while it does not occur in TiSi2 gates less than 5 mum long. From th ese results we found that the gate sheet resistance can not be reduced to less than 5 OMEGA/sq by conventional Ti salicide technology in gat es shorter than 0.4 mum due to increase in gate resistance caused by a gglomeration and lack of phase transition.