RECONFIGURING FAULT-TOLERANT 2-DIMENSIONAL ARRAY ARCHITECTURES

Authors
DAVIS NJ GRAY FG WEGNER JA LAWSON SE MURTHY V WHITE TS
Citation
Nj. Davis et al., RECONFIGURING FAULT-TOLERANT 2-DIMENSIONAL ARRAY ARCHITECTURES, IEEE MICRO, 14(2), 1994, pp. 60-69
Citations number
14
Categorie Soggetti
Computer Sciences","Computer Science Hardware & Architecture","Computer Science Software Graphycs Programming
Journal title
IEEE MICRO → ACNP
ISSN journal
02721732
Volume
14
Issue
2
Year of publication
1994
Pages
60 - 69
Database
ISI
SICI code
0272-1732(1994)14:2<60:RF2AA>2.0.ZU;2-2
Abstract
Circuit complexities reduce overall reliability and mean-time-between- failure rates of today's very large processing arrays. Our integrated, three-level hierarchy of reconfiguration methods provides reasonable levels of fault tolerance for such systems. Operating in a completely distributed fashion, the hierarchy does not require that any component s be fault free. It significantly improves array reliability by using a combination of transient fault rollback techniques and local and glo bal reconfiguration algorithms.