VLSI SYSTOLIC ARRAY FOR SRIF DIGITAL SIGNAL-PROCESSING ALGORITHM

Authors
Citation
K. Iwami et K. Tanaka, VLSI SYSTOLIC ARRAY FOR SRIF DIGITAL SIGNAL-PROCESSING ALGORITHM, IEICE transactions on fundamentals of electronics, communications and computer science, E77A(9), 1994, pp. 1475-1483
Citations number
NO
Categorie Soggetti
Engineering, Eletrical & Electronic","Computer Science Hardware & Architecture","Computer Science Information Systems
ISSN journal
09168508
Volume
E77A
Issue
9
Year of publication
1994
Pages
1475 - 1483
Database
ISI
SICI code
0916-8508(1994)E77A:9<1475:VSAFSD>2.0.ZU;2-U
Abstract
Kalman filter is an essential tool in signal processing, modern contro l and communications. The filter estimates the states of a given syste m from noisy measurements, using a mean-square error criterion. Althou gh Kalman filter has been shown to be very versatile, it has always be en computationally intensive since a great number of matrix computatio ns must be performed at each iteration. Thus the exploitation of this technique in broadband real time applications is restricted. The solut ion to these limitations appears to be in VLSI (very large scale integ ration) architectures for the parallel processing of data, in the form of systolic architectures. Systolic arrays are networks of simple pro cessing cells connected only to their nearest neighbors. Each cell con sists of some simple logic and has a small amount of local memory. Ove rall data flows through the array are synchronously controlled by a si ngle main clock pulse. In parallel with the development of Kalman filt er, the square root covariance and the square root information methods have been studied in the past. These square root methods are reported to be more accurate, stable and efficient than the original algorithm presented by Kalman. However it is known that standard SRIF is less e fficient than the other algorithms, simply because standard SRIF has a dditional matrix inversion computation and matrix multiplication which are difficult to implement in terms of speed and accuracy. To solve t his problem, we use the modified Faddeeva algorithm in computing matri x inversion and matrix multiplication. The proposed algorithm avoids t he direct matrix inversion computation and matrix multiplication, and performs these matrix manipulations by Gauss elimination. To evaluate the proposed method, we constructed an efficient systolic architecture for standard SRIF using the COMPASS design tools. Actual VLSI design and its simulation are done on the circuits of four type processors th at perform Gauss elimination and the modified Givens rotation.