ESTIMATE OF THE ULTIMATE PERFORMANCE OF THE SINGLE-ELECTRON TRANSISTOR

Citation
Mi. Lutwyche et Y. Wada, ESTIMATE OF THE ULTIMATE PERFORMANCE OF THE SINGLE-ELECTRON TRANSISTOR, Journal of applied physics, 75(7), 1994, pp. 3654-3661
Citations number
18
Categorie Soggetti
Physics, Applied
Journal title
ISSN journal
00218979
Volume
75
Issue
7
Year of publication
1994
Pages
3654 - 3661
Database
ISI
SICI code
0021-8979(1994)75:7<3654:EOTUPO>2.0.ZU;2-9
Abstract
The scaling limit of current semiconductor devices is thought to be ab out 100 nm. To reduce the size of devices beyond this point will proba bly require a new device technology. The metal single-electron transis tor, using the Coulomb blockade effect, has been proposed as a replace ment for semiconductor devices. Recently devices of this kind with pot entially useful properties have been fabricated. The scaling of such d evices down to atomic dimensions is investigated to see if they can co mpete with semiconductor logic or analog devices. It concentrates on t he operation of a single device and not on the effects of integration. Until now such models for the single-electron transistor have assumed that the capacitance and conductance of the various junctions can be chosen independently, but it is demonstrated that the physical geometr y causes restrictions on these choices. A second restriction is that a s the device is made smaller the capacitance drops. This means that th e temperature of operation rises, but so do the voltages required acro ss the device. A point is reached where these voltages exceed the brea kdown voltage of the junctions. For this reason the devices cannot be scaled indefinitely. The model predicts that if the devices are to per form logic functions or analog amplification their maximum speed will be limited to between 1 and 10 ps, which is not a great improvement on semiconductors, especially since for ultimate speed such devices will need to be 100 times smaller. The operation of such high-speed device s will not be possible at room temperature. Operation at 77 K will be possible but very difficult, and with current lithography limits of 10 nm, operation of useful logic even at 4.2 K will be marginal. The mod el does not rule out the use of the single-electron transistor for oth er purposes, such as memory and sensitive electrometers, and a process is described for the fabrication of 50 nm devices using a minimum of processing.