A BROAD-BAND FREQUENCY-SYNTHESIZER WITH INCREASED OPERATING SPEED

Frequency synthesizers (FS) in a phase-locked loop (PLL) design employ ing a variable-radio frequency divider (VRFD) in the feedback (FB) loo p and broadband frequency synthesizers based on two independent PLL de signs with a mixer have found wide commercial application in various r adio devices by virtue of their compact size and tuning simplicity [1, 2]. However, if a small tuning increment occurs in the spectrum of su ch a frequency synthesizer (see Fig. 1a) a high frequency-division rat io of the VFRD in the loop is required, which narrows the passband and in turn prolongs the transient in the frequency synthesizer for frequ ency switching and increases the phase noise in the output signal. Pha se noise within the passband of the PLL is determined by the low refer ence signal noise and is due to the high noise level of the tunable os cillator outside the passband [1]. Existing methods of increasing spee d and reducing phase noise (step transformation circuits and fractiona l division-ratio circuits) do not provide complete solutions to the pr oblem of obtaining an optimal passband. One way of improving the perfo rmance characteristics of a broadband frequency synthesizer by modifyi ng the method of establishing feedback without substantially complicat ing the circuit is examined in this paper.