A DELAY MODEL AND OPTIMIZATION METHOD OF A LOW-POWER BICMOS LOGIC-CIRCUIT

A new delay model and optimization method is proposed for a low-power BiCMOS driver. A transient overdrive, base directly-tied complementary BiCMOS logic circuit operates faster than conventional BiCMOS and CMO S circuits for supply voltage down to 1.5 V by using a speed-power-are a optimization approach. An analytical delay expression is derived for the first time for a full-swing BiCMOS circuit with short-channel eff ects. The circuit is simulated with a HSPICE model using 0.8-mu m BiCM OS technology with a 6-GHz n-p-n and a 1-GHz p-n-p transistor. The sim ulation results have verified the analytical results and demonstrated that the circuit can work up to 200 MHz operating frequency for a load capacitance of 1 pF at 1.5 V of supply voltage.