AN ASYNCHRONOUS GAAS-MESFET STATIC RAM USING A NEW CURRENT MIRROR MEMORY CELL

An experimental 1-kb GaAs MESFET static RAM using a new memory cell ha s been designed, fabricated and tested. The new memory cell is not sub ject to the destructive read problems that constrain the design of the conventional six-transistor memory cell. The biasing arrangement for this new cell minimizes the leakage currents associated with unselecte d bits attached to a column, maximizing the number of bits allowed per column. This new memory cell also provides a much larger access curre nt for readout than is possible using a conventional memory cell of th e same area and cell power. A write time of 1.0 ns and address access times of between 1.0 and 2.3 ns have been obtained from a 1-kb test ci rcuit. A cell area of 350 mu m(2) and cell current of 60 mu A were ach ieved using a conventional E/D process.