ON POLYNOMIAL-TIME TESTABLE COMBINATIONAL-CIRCUITS

Authors
Citation
Nsv. Rao et S. Toida, ON POLYNOMIAL-TIME TESTABLE COMBINATIONAL-CIRCUITS, I.E.E.E. transactions on computers, 43(11), 1994, pp. 1298-1308
Citations number
20
Categorie Soggetti
Computer Sciences","Engineering, Eletrical & Electronic","Computer Science Hardware & Architecture
ISSN journal
00189340
Volume
43
Issue
11
Year of publication
1994
Pages
1298 - 1308
Database
ISI
SICI code
0018-9340(1994)43:11<1298:OPTC>2.0.ZU;2-K
Abstract
The problems of identifying several nontrivial classes of Polynomial-T ime Testable (PTT) circuits are shown to be NP-complete or harder. Fir st, PTT classes obtained by using circuit decompositions proposed by F ujiwara and Chakradhar et al. are considered. Another type of decompos itions, based on fanout-reconvergent (f-r) pairs, which also lead to P TT classes are proposed. The problems of obtaining these decomposition s, and also some structurally similar general graph decompositions, ar e shown to be NP-complete or harder. Then, the problems of recognizing PTT classes formed by the Boolean formulae belonging to the weakly po sitive, weakly negative, bijunctive and affine classes (proposed by Sc haefer) are shown to be NP-complete.