A CONCURRENT TEST ARCHITECTURE FOR MASSIVELY-PARALLEL COMPUTERS AND ITS ERROR-DETECTION CAPABILITY

This paper presents new principles for the on-line monitoring in the c ontext of multiprocessors (especially massively parallel processors) a nd then focuses on the effect of the aliasing probability on the error detection process. In the proposed test architecture, the concurrent testing (or on-line monitoring) at system level is accomplished by enf orcing the runtime test of the data and control dependences of the alg orithm currently executed in the parallel computer. In order to help i n this process, each message contains both source and destination addr esses. At each message source, the sequence of destination addresses o f the outgoing messages is compressed on a block basis. At the same ti me, at each destination; the sequence of source addresses of all incom ing messages is compressed, also on a block basis. Concurrent compress ion of the instructions executed by the PE's is also possible. As a re sult of this procedure, an image of the data dependences and bf the co ntrol flow of the currently run algorithm is created. This image is co mpared at the end of each computational block with a reference image c reated at compilation time. The main results of this work are in propo sing new principles for the on-line system-level test of multiprocesso rs systems,based on signaturing and monitoring the data dependences to gether with the control dependences, and in providing an analytical mo del and analysis for the address compression process used for the moni toring the data routing process.