TECHNOLOGY DESIGN FOR HIGH-CURRENT AND ESD ROBUSTNESS IN A DEEP-SUBMICRON CMOS PROCESS

The intrinsic ESD/EOS robustness of a technology is determined by the sensitivity to thermal initiated second breakdown. We show, for the fi rst time, high current and ESD robustness results for a deep submicron CMOS technology with drawn poly gate lengths of 0.35 mu m and oxide t hicknesses down to 4.5 nm. It is shown that a transistor design window can be determined for optimized drive current and good robustness, wh ile maintaining low off currents. An important observation is that rob ustness increases for smaller channel lengths and is directly proporti onal to the transistor drive current. Hence, robust deep submicron tec hnologies can be designed with optimized transistor performance withou t using additional masks or increasing process complexity.