PARALLEL CONTROLLER SYNTHESIS FOR PROGRAMMABLE LOGIC DEVICES

The standard approach to parallel controller design uses sequential co ntroller design techniques. However, since these techniques cannot rep resent concurrent states, the problem must first be partitioned and th en designed as a number of linked finite state machines. This initial partitioning is usually non-optimum and limits the amount of concurren cy in the subsequent design, where the interaction between the finite state machines also makes verification difficult. This paper presents an alternative technique for parallel controller design in which a syn chronous, interpreted Petri net is used to model the controller's spec ification as a single parallel network. No pre-partitioning is necessa ry, and the amount of concurrency dynamically reflects the amount of p arallel activity on the data path. The formalism provided by the techn ique also reduces the likelihood of parallel synchronization errors. T he technique is illustrated with the design of a parallel controller f or a transputer link adapter and its implementation on a programmable logic device.