TRANSLATION OF VHDL FOR LOGIC SYNTHESIS

Logic synthesis can be achieved from the majority of VHDL, but some co nstructs have to be restricted. The techniques used in the TransGATE s ystem to synthesize VHDL are explained. These ideas will be useful for those who wish to understand the process of designing hardware from V HDL models. It should be noted that the semantic completeness of VHDL extends only to constrain simulation tools and not to synthesis. Thus, techniques for hardware implementation described here will not necess arily be the same as other synthesis tools use. The main consideration for users of synthesis tools is to develop the design using a synchro nous design methodology since there is no capability as yet for asynch ronous circuit synthesis. With this restriction, synthesis can be used in the design of combinational logic processes, registered logic proc esses or finite state machines.