OPTIMIZATION OF ULTRATHIN GATE OXIDE IN A SILO RTN ISOLATION PROCESS FOR ADVANCED ULSI - INTRODUCING A NEW CONCEPT OF SURFACE GETTERING/

Ultrathin gate oxide (5 to 7 nm) optimization is performed by integrat ion into a SILO/RTN isolation process. The influence of initial condit ions on gate oxide defect density and QBD is studied. The gate oxide q uality is monitored by the RTN temperature weighed by substrate type a nd initial oxygen content, epi layer, and the cleaning step before RTN . A new concept of surface monolayer gettering is introduced to explai n why a last oxide monolayer before RTN is efficient for contamination trapping on Czochralski grown silicon. A comparison is done between b ulk and epi substrate results. In Czochralski material, a maximum oxyg en concentration is found to avoid the negative impact of residual oxy gen on metal ions trapping during the RTN step. The electrical results are correlated to surface and TEM analysis. The sacrificial oxidation optimization is performed as a function of thickness and temperature with O2 + HCl based oxidation. A minimum temperature (950-degrees-C) a nd a minimum thickness (45 nm) are found to minimize defect density an d maximize QBD. Standard LOCOS and SILO/RTN isolations are compared. F inally, the possibility of using this isolation on advanced CMOS is de monstrated.