GLOBAL DESIGN OF ANALOG CELLS USING STATISTICAL OPTIMIZATION TECHNIQUES

We present a methodology for automated sizing of analog cells using st atistical optimization in a simulation based approach. This methodolog y enables us to design complex analog cells from scratch within reason able CPU time. Three different specification types are covered: strong constraints on the electrical performance of the cells, weak constrai nts on this performance, and design objectives. A mathematical cost fu nction is proposed and a bunch of heuristics is given to increase accu racy and reduce CPU time to minimize the cost function. A technique is also presented to yield designs with reduced variability in the perfo rmance parameters, under random variations of the transistor technolog ical parameters. Several CMOS analog cells with complexity levels up t o 48 transistors are designed for illustration. Measurements from fabr icated prototypes demonstrate the suitability of the proposed methodol ogy