A 1.5-NS 256-KB BICMOS SRAM WITH 60-PS 11-K LOGIC GATES

A 1.5-ns address access time, 256-kb BiCMOS SRAM has been developed. T o attain this ultra-high-speed access time, an emitter-coupled logic ( ECL) word driver is used to access 6-T CMOS memory cells, eliminating the ECL-MOS level-shifter time delay. The RAM uses a low-power active pull down ECL decoder. The chip contains 11-K, 60-ps ECL circuit gates . It provides variable RAM configurations and general logic functions. RAM power consumption is 18 W; chip power consumption is 35 W. The ch ip is fabricated by using; a 0.5-mu m BiCMOS process. The memory cell size is 58 mu m(2) and the chip size is 11 x 11 mm.