HIGH-SPEED, LOW-SWITCHING NOISE CMOS MEMORY DATA OUTPUT BUFFER

This paper describes a data output buffer for highspeed CMOS integrate d memories with a high data output pin count. The buffer minimizes the switching noise induced on supply lines while achieving very fast out put transitions by combining output presetting techniques together wit h adequate driving of the output pull-up and pull-down transistors. Tr istate operation and zero static power consumption are also provided. The buffer was integrated in a 16-Mb EPROM device. It occupies 0.06 mm (2) and ensures a better than 15 ns output transition time with a load capacitor of 100 pF.