A 3-V, 22-MW MULTIBIT CURRENT-MODE SIGMA-DELTA DAC WITH 100 DB DYNAMIC-RANGE

The area ratio of analog to digital for mixed-mode chip has been inver sely proportional to the process design rule for a given dynamic range objective, in contradiction to the LSI trend. This paper presents a d esign approach to realize a high degree of size reduction with process design rules for analog circuitry and a signal processing architectur e for digital circuitry. A five-level current-mode Sigma Delta digital -to-analog converter (DAC) system reveals full scale total harmonic di stortion plus noise (THD + N) of -90 dB and dynamic-range of 100 dB at 3 V (low power of 22 mW). Analog-area down-scaling cars be accomplish ed by this architecture to be 1.09 mm(2), using 0.6-mu m double-poly d ouble-metal (DPDM) CMOS. Far the digital filter, a pipeline instructio n sequence with multiplierless architecture also gives small area of 1 .98 mm(2)