2.8-GB S 176-MW BYTE-INTERLEAVED AND 3.0-GB/S 118-MW BIT-INTERLEAVED 8/1-MULTIPLEXER WITH A 0.15-MU-M CMOS TECHNOLOGY/

This paper reports the first CMOS implementation of an 8:1 byte-interl eaved multiplexer (byte-MUX) operating in the Gb/s region, together wi th an 8:1 hit-interleaved multiplexer (bit-MUX). A future generation 0 .15-mu m CMOS technology has been applied, Both chips use identical bi t-MUX cores with a static shift-register architecture; and have ECL in terfaces with a single supply of -2 V. The byte-MUX demonstrates 43-mW /GHz dependence can clock frequency and operates up to 2.8 Gb/s with a power dissipation of 176 mW. The bit-MUX showed 20-mW/GHz dependence on clock frequency and operated up to 3.0 Gb/s with ii power dissipati on of 118 mW. This Bevel of performance has been achieved by a novel r ow-column exchanger configuration, critical path reduction sind precis e clocking techniques utilized in the bit-MUX core, and the developmen t of high-speed I/O buffers.